1. Field of the Invention
The present invention relates to a DC/DC converter that converts a voltage input thereto to a predetermined voltage for output, and more particularly to a DC/DC converter that produces the desired output voltage from the input voltage by first finding the error voltage between the output voltage and a first reference voltage and then controlling the output current according to the differential voltage between the error voltage and a second reference voltage.
2. Description of the Prior Art
Some conventional DC/DC converters use a soft-start capacitor, as exemplified by the one disclosed in Japanese Patent Application Laid-Open No. H7-298614.
Such a DC/DC converter is thereby not only protected against an overcurrent but also made capable of preventing a rush current from flowing into the load at start-up.
However, in the DC/DC converter described above, when the error voltage Vith (a voltage obtained by amplifying the differential voltage between the output voltage Vo and an output voltage setting reference voltage Voref) is compared with an output current setting reference voltage Viref to control the output voltage Vo, because this reference voltage Viref is constant and in addition because a CR circuit used for phase compensation (for prevention of oscillation) makes blunt the rise of the error voltage Vith at start-up, it takes a considerable time for the error voltage Vith to reach the reference voltage Viref as shown in FIGS. 5A and 5B. During the period in which the error voltage Vith is lower than the reference voltage Viref, the DC/DC converter can produce only an output current “io” of negative (or extremely low) magnitude. This produces, immediately after start-up, a period in which the output voltage Vo does not rise. This delay in the rise of the output voltage Vo allows the charging of the soft-start capacitor to proceed, raising its terminal voltage Va (a variable reference voltage for achieving soft starting that, only at the initial stage of start-up, substitutes for the reference voltage Voref so as to be compared with the output voltage Vo). Thus, when the error voltage Vith eventually reaches the reference voltage Viref, there already is a great difference between the output voltage Vo and the terminal voltage Va, with the result that the output voltage Vo rises comparatively abruptly.
Thereafter, when the output voltage Vo rises until it reaches the terminal voltage Va (or the constant reference voltage Voref), the error voltage Vith starts falling. Also here, as described above, the phase compensation CR circuit makes blunt the fall of the error voltage Vith. Thus, it takes a considerable time for the error voltage Vith to become lower than the output current setting reference voltage Viref. Accordingly, the DC/DC converter produces an excessive output current “io” even after the output voltage Vo has reached the terminal voltage Va (or the constant reference voltage Voref), possibly causing an overshoot in the output voltage Vo. Such an overshot in the output voltage Vo needs to be prevented or reduced as much as possible, because it may put a burden on the output transistor and the load not only, needless to say, when its peak level exceeds the constant reference voltage Voref but also even when it does not.
Furthermore, the DC/DC converter described above gives no consideration to an undershoot in the output voltage Vo at shut-down.